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With energy efficiency creeping up enterprises’ evaluation criteria list, Intel knew it couldn’t afford to allow its future chips to use more power.

The Santa Clara, Calif., company went back to the drawing board to create a new chip architecture—a replacement for the circuitry that underpins its entire x86 product line—that would both increase performance and cut power consumption.

“Energy is on everyone’s mind,” said Intel Chief Technology Officer Justin Rattner during a keynote at the March Intel Developer Forum in San Francisco, where he announced the architecture. “There’s a fundamental tension here between performance and energy consumed. It’s a classic trade-off.”

Touting greater energy efficiency—and, no doubt, attempting to thwart Advanced Micro Devices, which has been making headway in servers as of late—Intel will roll out three dual-core chips based on the new Intel Core Microarchitecture later this year.

At the heart of the circuitry is an idea that Intel’s chips shouldn’t necessarily be faster—indeed, speedier chips also generally consume more power—but that they should get more work done per clock cycle.

One major change along these lines was the addition of the ability to execute four instructions in a single clock cycle.

“That has given us the ability to get more done in fewer cycles,” said Rattner. “By doing so, we consume less power.”

Intel also chose to use a 14-stage pipeline, and designers cut onboard cache access times and beefed up the ways in which data is prefetched from system memory to ensure that processor cores aren’t kept waiting.

Pipeline length is an important factor for processor performance as well as for power consumption. But longer pipelines breed higher clock speeds, meaning those chips might use more power.

Intel therefore sought to strike a balance. The 14-stage pipeline is slightly longer than the “Banias” architecture behind the company’s Core Duo notebook chip, which has 12 stages. But it’s still about half the length of later Pentium 4 processors, which process only between one and three instructions per clock cycle.

Several other Intel Core Microarchitecture features serve to get more done per clock cycle, said Rattner, including speedier Intel SSE (Streaming SIMD Extensions) multimedia instruction processing and consolidating certain small instructions to process as one.

Another trick allows the parts of a chip that are not needed immediately to shut down to save power, Rattner added.

The new architecture will allow chips such as Intel’s dual-core “Woodcrest” server processor, due in the third quarter, to offer a 35 percent reduction in power consumption with an 80 percent bump in performance over the current Xeon DP processor, Rattner said.