Samsung wants to shrink one of AI infrastructure’s biggest bottlenecks: the distance between processors and memory.
At FMS 2026 in Santa Clara, California, the company previewed zHBM and zNAND-O concept architectures, introduced its 400-plus-layer V10 BV-NAND design and outlined a roadmap spanning HBM4E, HBM5 and enterprise storage. Samsung says the technologies could increase bandwidth, capacity and power efficiency across future AI systems, although it has not announced commercial availability for the new concepts.
For solution providers and infrastructure partners, the roadmap points to denser and more tightly integrated AI platforms — but also to new requirements around cooling, packaging, system compatibility and customer-specific chip design.
zHBM moves memory closer to AI processors
Samsung’s zHBM concept represents a shift from today’s high-bandwidth memory designs, where memory is placed alongside processors. Instead, the company’s approach vertically stacks HBM directly above AI accelerators.
The design aims to reduce the distance data must travel between memory and processors, potentially improving bandwidth and lowering power requirements for AI training and inference workloads.
Samsung projects that a future interface using zHBM could deliver about 8x the performance of HBM5. The company also said next-generation wafer bonding could enable more than 10x the memory density, three times the energy efficiency and less than half the thermal resistance of HBM5. The company did not provide independent benchmarks or a commercialization timeline.
The architecture also supports custom designs by allowing customer-specific intellectual property to be integrated between the memory and AI accelerator.
Samsung’s second 3D concept, zNAND-O, targets edge AI environments. Built on the company’s V-NAND technology, the storage architecture is being developed in four- and eight-layer versions and is designed to deliver lower latency, improved input/output performance and greater space efficiency for real-time AI applications.
V10 BV-NAND Pushes Beyond 400 Layers
Samsung also introduced V10 BV-NAND, its new Bonding V-NAND architecture and the company’s first NAND technology with more than 400 layers.
According to Samsung, the technology uses wafer bonding to stack memory cells and increases density by about 58% compared with its previous-generation V9 technology. The company said V10 BV-NAND also improves read, write and I/O performance.
The announcement comes 13 years after Samsung introduced its original V-NAND technology at the 2013 Flash Memory Summit, marking another step in the company’s effort to increase storage capacity for AI systems.
Samsung expands AI memory portfolio
Beyond its new concepts, Samsung showcased a broader AI memory lineup that includes HBM4E, HBM5, LPDDR5X-PIM and enterprise storage solutions such as PM1763 and BM1773.
Samsung said it began mass production of HBM4 using its 1c DRAM and 4nm base die technologies in February and started shipping HBM4E samples to global customers in May.
The company also highlighted LPDDR5X-PIM, which brings processing-in-memory capabilities to LPDDR memory. Instead of sending all data back and forth between memory and processors, PIM technology allows some processing tasks to happen inside memory, reducing data movement and potentially improving efficiency.
The bigger AI hardware race
Samsung’s announcements show how memory has become a central battleground in AI infrastructure. As AI models grow larger, performance is increasingly limited not only by computing power but also by how quickly systems can access and move data.
The company is positioning its memory, foundry and advanced packaging capabilities as a more integrated AI hardware supply chain. Samsung said its integrated device manufacturer model allows customers to develop and manufacture customized AI semiconductor solutions through one provider.
However, these technologies remain forward-looking. Concept architectures such as zHBM and zNAND-O will need to overcome manufacturing complexity, cost challenges and ecosystem adoption before they become widely available. While improved memory efficiency could help AI companies build larger and faster systems, the benefits will depend on whether software, processors and data center designs evolve alongside the hardware.
Read more: How rising memory and storage prices are affecting channel partners’ procurement strategies, customer budgets and storage decisions.