Chip Makers to Outline Road MapsBy Jeffrey Burt | Posted 2006-10-10 Email Print
WEBINAR: Event Date: Tues, December 5, 2017 at 1:00 p.m. ET/10:00 a.m. PT
How Real-World Numbers Make the Case for SSDs in the Data Center REGISTER >
Performance increases and power management will be key issues at the Microprocessor Forum, where IBM will tout Power6 while AMD will talk up quad-core Opterons.The industry is getting a glimpse of the not-so-distant future for microprocessors.
At the Microprocessor Forum in San Jose, Calif., Oct. 10, engineers from Advanced Micro Devices, IBM, Fujitsu and Sun Microsystems will give presentations about their new generation of processors that will be released in 2007.
Key to all the work being done is the need to pump up the performance of the chips while keeping the energy consumption relatively level with the current processors, said Charles King, an analyst with Pund-IT Research.
Brad McCredie, IBM fellow and chief engineer for Power6, said that at his Microprocessor Forum presentation he won't be more specific about the chip's speedengineers are hitting their frequency targets in tests but haven't decided what the points will be when it shipsbut instead will focus on flexibility and reliability features, as well as some of the system energy management offerings.
"Customers have all said they don't really care what frequency the chips come in at," McCredie said in an interview with eWEEK before the conference. "They care about performance improvement. They want to know that the hardware will improve the performance of their applications."
Power6, built using IBM's 65-nanometer manufacturing process, rather than the current 90-nm, doubles the frequency of its predecessor but keeps the instruction pipeline at the same depth, rather than growing it, which is how most chip makers often speed up chips. The move means that IBM is able to crank up the speed without adding to the amount of time it takes for an instruction to get through a computation, which inhibits performance.
IBM also is integrating decimal floating point accelerators into the processor, which improves the performance of applications that involve decimals. Normally such work is done through software, McCredie said.
"Doing anything in software takes a lot of instruction and a lot of cycles," hindering application performance, he said. In one test, with telecommunication billing software, application performance improved by four to seven times, he said.
Reliability features include the chip's ability to check every computation in the processor and to automatically retry errors. If the retry works, then the computation continues. If there is consistent failure, then the workload is moved to another CPU.
IBM also is designing flexibility into the chip so that it can run in systems both large and small, playing into IBM's eCLipz plan to have a common processor architecture for its widespread server lines, including Systems i, p and z. The 65-nm manufacturing process plays into the energy efficiency, McCredie said. In addition, the chip can be configured for high or low voltage depending on the application needs, enabling the platform to scale, he said.
There also are multiple memory controller, SMP bus and Level 3 cache configurations, he said. In addition, Power6 will feature high-bandwidth memory and fabric I/O, which will help scale the processor.
"We can scale the chip up and down the server product line," he said.
As for virtualization, Power6 will be able to support up to 1,024 partitions and the virtual partitioning of memory.
Pund-IT analyst King said IBM appears to be making the right moves with Power6.
"Doubling the performance without increasing the power envelope is pretty amazing news," he said, adding that the other features are important as well, such as bringing floating-point capabilities onto the hardware. "It's not just more speed, but it allows people to do the kind of business they couldn't have done before."
It also illustrates the work that is still ahead of Intel as it works to improve its Itanium 2 processor. Intel, of Santa Clara, Calif., this year released its first dual-core chip, dubbed "Montecito," which supporters said brought the architecture in line with Power5 capabilities. Power6 is an indication that "the benefits of Montecito could be short-lived," King said.
Next Page: The battle for quad-core.
Barcelona also will offer a Level 3 cache that will be shared by all the processing cores, which will complement the L2 cache that each core has. The shared cache will be particularly beneficial to large applications that need access to the same data stored there, said Chuck Moore, a senior fellow at AMD.
Other enhancements include better DRAM efficiency through independent controllers and larger buffering in the Northbridge and memory controller, Sander said. Also, virtualization support and security are improved, making application performance in virtualized environments "closer to native performance" in physical servers, Sander said.
Power management features include separate power planes for the processing core and integrated Northbridge, which enables the cores to throttle down power depending on application demand while keep the Northbridge powered up. In addition, with an enhanced PowerNow offering, each core can be dynamically controlled depending on workload demand.
AMD's presentation will come a month after rival Intel outlined its quad-core plans at its fall developer forum. Intel announced plans to bring its first quad-core chips to market this fall.
A key difference is Intel's initial quad-core chips will essentially feature two dual-core chips on a single piece of silicon, enabling the chip maker to beat AMD to market. However, AMD officials have argued that the company's native quad-core chips with its on-board memory will be more elegant and efficient than Intel's offerings.
Also presenting at the Microprocessor Forum Oct. 10 will be Sun and Fujitsu. Sun, of Santa Clara, Calif., will outline plans for "Niagara 2," the follow-on to its multicore UltraSPARC T1 processor. Like the first Niagara, Niagara 2, due next year, will feature up to eight cores. However, each core will be capable of running up to eight instruction threads simultaneously, doubling the capacity of the current chip.
For Tokyo-based Fujitsu, its upcoming Sparc64 VI will be its first dual-core offering and will be the basis for the upcoming Advanced Product Line of servers, developed jointly with Sun.
Check out eWEEK.com's for the latest news, views and analysis on servers, switches and networking protocols for the enterprise and small businesses.