Cadence CTO Calls for Power Savings in Chip DesignBy Daniel Drew Turner | Posted 2006-10-11 Email Print
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The CTO of Cadence Design Systems says the microprocessor industry needs to develop a common power format that will allow chip designers to improve efficiency and reduce power consumption in future models.SAN JOSE, Calif.Asserting that power consumption consideration is "not a first-class citizen" in the current state of microprocessor design, Ted Vucurevich, chief technology officer of Cadence Design Systems, said the industry needs a common power format to help optimize power versus performance in future designs.
He made his remarks at the Microprocessor Forum here, which was dedicated to the topic "Advances in Power EfficiencyAddressing the Global Challenge."
A common power format, or CPF, Vucurevich said, would help alleviate the "mess" that faces chip designers when trying to reduce power levels. The CPF concept is currently being promoted by an industry coalition that includes Cadence, Freescale, Advanced Micro Devices, ARM, Fujitsu, ATI and others.
Last year marked the crossover point where more silicon went into consumer devices than into machines dedicated to pure computation, he said. "This is due to embedded devices, in part" he said, including signal processing chips, dedicated graphical processor units and similar processors.
This creates "a market window that continues to shrink," he said. That is, chip makers and device manufacturers are pushing to move their products to market more rapidly. But this allows less time for testing and revising microprocessor designs, if the basic design requires improvement.
As a result, he said, many of the challenges in chip design move "upstream," away from the traditional synthesis and placement stages, where much of the validation usually takes place, to the earlier architecting and RTL (register transfer logic) stages.
"Design models need to be stronger," Vucurevich said, "and we need more robust designs."
"Low power requires you to think about a lot more things that complicate your design," he said. These issues include listing voltage isolation, state retention, clock gating and multithreshold voltages.
These new challenges, he said, require a tighter interconnection of hardware and software design, as well as a more formal way to deal with power at the design stage. Currently, he said, solving power issues can be thrown in as design suggestions, or later in the manufacturing process as a byproduct of trying to minimize die size, or at many other points. "There's no formalism," he said.
Partly, he said, this is due to a lag in automated chip design software, which currently does not fully automate power factors. Vucurevich noted that such factors as synthesis, testing, simulation and virtual prototyping often are not handled in a consistent manner among chip designers. "This makes it very difficult to automate," he said.
But with a CPF, he said, automated chip design software can assign parsers to these factors and streamline the process. Vucurevich said ARM used an automated design process that took power-saving factors into account to design a test chip that achieved a 40 percent overall power reduction and a similar decrease in power leakage compared with typical design processes.
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