AMD Offers Performance Details of New Dual-Core Opteron

By Mark Hachman  |  Posted 2004-10-05 Email Print this article Print
 
 
 
 
 
 
 

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AMD unveils its dual-core Opteron architecture at the Fall Processor Forum, along with its first performance estimates.

SAN JOSE, Calif.—Advanced Micro Devices Inc. on Tuesday unveiled its dual-core architecture here at In Stat/MDR's Fall Processor Forum and provided the first estimates of the chip's performance.

As the company previously stated, AMD's first dual-core chips for one to-eight way servers will be "first to market" in 2005. Company executives said client-specific versions are due in the second half. Kevin McGrath, an AMD fellow, noted that the company's dual-core architecture built on the groundwork laid by AMD's "Hammer" processor—now known as the AMD Opteron— introduced several years ago.

McGrath said AMD processors with two or more cores could power home PCs or servers that could simultaneous stream audio and video to separate rooms, while a third user worked on a presentation.

"Five years ago AMD gave you a hammer," McGrath said. "Now we're giving you a complete new toolbox. Use it and enjoy it," he told system vendors in the audience.

McGrath also answered key questions about the performance of the dual-core chips compared to their single-core cousins. To minimize power under 95 watts, the dual-core chips will be under-clocked. As part of his presentation, McGrath compared the performance of dual-core chips versus a standard two-way, unicore system.

A two-processor dual-core system clocked 5 clock speeds down from AMD's fastest part will generate performance of approximately 125 to 140 percent performance of the dual-processor unicore system, McGrath said.

For example, a dual-core, dual-processor system clocked at only three grades slower than the fastest AMD chip will perform at between 130 to 160 percent of the performance of the base system, McGrath's slide indicated. McGrath's performance figures used synthetic benchmarks, such as SPECint_rate 2000 and SPECifp_rate 2000.

Each individual core will contain 1MB of Level 2 cache, McGrath said. Memory requests will be piped through a system request interface to a crossbar switch. The original Opteron and Athlon 64 design was designed with multiple cores in mind, he reminded the audience.

Both cores will share a single memory controller, which may prove problematic in future generations, analysts noted. For now, the memory controller will access 128-bit DDR-1 memory. Three HyperTransport or "DirectConnect" links will tie the dual-core chip to the rest of the system.

Future versions of the dual-core Opteron-Athlon 64 chips may contain two or more memory controllers to keep the processors fed with instructions, McGrath added.

To read the full ExtremeTech story, click here.

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